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1 ? fn8202.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyright intersil americas inc. 2004, 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. x9455 dual two-wiper di gitally-controlled (xdcp?) potentiometer the x9455 integrates 2 digita lly controlled potentiometers (xdcp), each one with dual wip ers, on a monolithic cmos integrated circuit. the digitally controlled potentio meter is implemented using 255 resistive elements in a series array. between each element are tap points connected to wiper terminals through switches. the position of each wiper on the array is controlled by the user th rough the u/d or 2-wire bus interface. each potentiometer wip er has associated with it two volatile wiper counter register (wcr) and each wcr has associated with it four non-volatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. the contents of the default data registers (dr0a0, dr0b0, dr1a0, dr1b0) are loaded into the wcr on power up. the dcp can be used as a four-t erminal potentiometer in a wide variety of applications in cluding the programming of bias voltages, window comparators, and three resistor programmable networks. features ? dual two-wiper solid state potentiometer ? 256 resistor tap points-0.4% resolution ? 2-wire serial interface for write, read, and transfer operations of the potentiometer ? up/down interface for individual potentiometer wipers ? wiper resistance, 40 typical ? non-volatile storag e of wiper positions ? power on recall loads saved wiper position on power-up. ? standby current < 20a max ? maximum wiper current: 3ma ?v cc : 2.7v to 5.5v operation ?2.8k ,10k , 50k , 100k version of total pot resistance ? endurance: 100,000 data changes per bit per register ? 100 yr. data retention ? 24 ld tssop ? pb-free plus anneal available (rohs compliant) pinout x9455 (24 ld tssop) top view rh1 nc rw1a 1 2 3 4 5 6 7 14 20 19 18 17 16 15 x9455 ds0 ds1 a0 rw0b u/d nc scl rl1 vss nc rw0a cs rh0 rl0 rw1b nc vcc 8 9 10 13 wp a2 11 12 sda a1 24 23 22 21 data sheet july 28, 2006 n o t r e co m m e nd e d f o r ne w d e s i g ns n o re c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - int e r s i l o r w w w . i n t e r s il . c o m / t s c
2 fn8202.1 july 28, 2006 functional diagram ordering information part number part marking v cc limits (v) r total (k ) temp range (c) package pkg. dwg. # x9455tv24i-2.7 x9455tv g 2.7 to 5.5 100 -40 to 85 24 ld tssop (4.4mm) mdp0044 x9455tv24iz-2.7 (note) x9455tv zg -40 to 85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9455uv24i-2.7 x9455uv g 50 -40 to 85 24 ld tssop (4.4mm) mdp0044 x9455uv24iz-2.7 (note) x9455uv zg -40 to 85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9455wv24i-2.7 x9455wv g 10 -40 to 85 24 ld tssop (4.4mm) mdp0044 x9455wv24iz-2.7 (note) x9455wv zg -40 to 85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9455yv24i-2.7 x9455yv g 2.8 -40 to 85 24 ld tssop (4.4mm) mdp0044 x9455yv24iz-2.7 (note) x9455yv zg -40 to 85 24 ld tssop (4.4mm) (pb-free) mdp0044 note: intersil pb-free plus anneal products em ploy special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. v cc v ss 2-wire r w0a a0 a1 sda scl cs u/d a2 ds0 ds1 wp wcr0a dr0a0 dr0a1 dr0a2 dr0a3 r h0 r l0 dcp0 wcr0b dr0b0 dr0b1 dr0b2 dr0b3 r w0b r w1a wcr1a dr1a0 dr1a1 dr1a2 dr1a3 r h1 r l1 dcp1 wcr1b dr1b1 dr1b2 dr1b3 r w1b powerup, interface control and status interface up/down interface dr1b0 x9455
3 fn8202.1 july 28, 2006 pin descriptions tssop pin symbol brief description 1 ds0 wiper selection input for up/down interface 2 a0 device address for 2-wire interface 3 rw0b second wiper terminal of dcp0 4 nc no connect 5 nc no connect 6u/d increment/decrement for up/down interface 7 vcc system supply voltage 8 rl0 low terminal of dcp0 9 rh0 high terminal of dcp0 10 rw0a first wiper terminal of the dcp0 11 a2 device address for 2-wire interface 12 wp hardware write protect (active low) 13 sda serial data input/output for 2-wire interface 14 a1 device address for 2-wire interface 15 nc no connect 16 nc no connect 17 rw1b second wiper terminal of dcp1 18 vss system ground 19 cs chip select for up/down interface 20 rw1a first wiper terminal of dcp1 21 rh1 high terminal of dcp1 22 rl1 low terminal of dcp1 23 scl serial clock for 2-wire interface 24 ds1 wiper selection input for up/down interface x9455
4 fn8202.1 july 28, 2006 absolute maximum ratings recommended operating conditions junction temperature under bias. . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c voltage at any digital interface pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v voltage at any dcp pin with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to v cc lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300 c i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v cc ) (note 4) limits . . . . . . . . . . . . . . 2.7v to 5.5v caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog specifications over recommended operating condi tions unless otherwise stated. symbol parameter test conditions min typ (note 4) max unit r total end to end resistance y, w, u, t ve rsions respectively 2.8, 10, 50, 100 k end to end resistance tolerance -20 +20 % power rating 25c, each dcp 50 mw r total matching dcp to dcp resistance matching 0.75 2.0 % i w (note 5) wiper current see test circuit -3.0 +3.0 ma r w wiper resistance wiper current = 50 150 v term voltage on any dcp pin vss vcc v noise (note 5) ref: 1khz -120 dbv resolution 0.4 % absolute linearity (note 1) v(r h0 )=v(r h1 )=v cc v(r l0 )=v(r l1 )=v ss -1 +1 mi (note 3) relative linearity (note 2) -0.3 +0.3 mi (note 3) temperature coefficient of resistance (note 5) 300 ppm/ c ratiometric temperature (note 5) coefficient -20 +20 ppm/c c h /c l /c w potentiometer capacitance (note 5) see equivalent circuit 10/10/25 pf i ol leakage on dcp pins voltage at pin from v ss to v cc 0.1 10 a v cc r total dc electrical specifications over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min max units i cc1 v cc supply current (volatile write/read) f scl = 400khz; sda = open; (for 2-wire, active, read and volatile write states only) 3ma i cc2 v cc supply current (active) f scl = 200khz; (for u/d interface, increment, decrement) 3ma i cc3 v cc supply current (nonvolatile write) f scl = 400khz; sda = open; (for 2-wire, active, nonvolatile write state only) 5ma i sb v cc current (standby) v cc = +5.5v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) 20 a i l leakage current, bus interface pins voltage at pin from v ss to v cc -10 10 a x9455
5 fn8202.1 july 28, 2006 v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage -1 v cc x 0.3 v v ol sda pin output low voltage i ol = 3ma 0.4 v dc electrical specifications over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min max units endurance and data retention parameter min units minimum endurance 100,000 data changes per bit data retention 100 years capacitance symbol test test conditions max units c in/out (note 5) input / output capacitance (sda) v out = 0v 8 pf c in (note 5) input capacitance (ds0, ds1, cs , u/d , scl, wp , a2, a1 and a0 ) v in = 0v 6 pf power-up timing symbol parameter max units t d (notes 5, 9) power up delay from v cc power up (v cc above 2.7v) to wiper position recall completed, and communication interfaces ready for operation. 2ms a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing threshold level v cc x 0.5 external load at pin sda 2.3k to v cc and 100 pf to v ss 2-wire interface timing (s) symbol parameter min max units f scl clock frequency 400 khz t high clock high time 600 ns t low clock low time 1300 ns t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:sto stop condition setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r (note 5) scl and sda rise time 300 ns t f (note 5) scl and sda fall time 300 ns t aa (note 5) scl low to sda data output valid time 0.9 s t dh sda data output hold time 0 ns t in (note 5) pulse width suppression time at scl and sda inputs 50 ns t buf (note 5) bus free time (prior to any transmission) 1200 ns x9455
6 fn8202.1 july 28, 2006 sda vs. scl timing wp , a0, a1, and a2 pin timing t su:wpa (note 5) a0, a1, a2 and wp setup time 600 ns t hd:wpa (note 5) a0, a1, a2 and wp hold time 600 ns 2-wire interface timing (s) (continued) symbol parameter min max units t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:wp scl sda in wp , a0, a1, or a2 t su:wp clk 1 start stop increment/decrement timing symbol parameter min typ (note 4) max units t ci cs to scl setup 600 ns t id (note 5) scl high to u/d , ds0 or ds1 change 600 ns t di (note 5) u/d , ds0 or ds1 to scl setup 600 ns t il scl low period 2.5 s t ih scl high period 2.5 s t ic scl inactive to cs inactive (nonvolatile store setup time) 1 s t cphs cs deselect time (store) 10 ms t cphns (note 5) cs deselect time (no store) 1 s t iw (note 5) scl to r w change 100 500 s t cyc scl cycle time 5 s t r , t f (note 5) scl input rise and fall time 500 s x9455
7 fn8202.1 july 28, 2006 increment/decrement timing notes: 1. absolute linearity is utilized to determine ac tual wiper voltage versus expected voltage = [v(r w(n)(actual) )-v(r w(n)(expected) )]/mi v(r w(n)(expected) ) = n(v(r h )-v(r l ))/255 + v(r l ), with n from 0 to 255. 2. relative linearity is a measure of the error in step size between taps = [v(r w(n+1) )-(v(r w(n) ) + mi)]/mi, with n from 0 to 254 3. 1 ml = minimum increment = [v(r h )-v(r l )]/255. 4. typical values are for t a = 25c and nominal supply voltage. 5. this parameter is not 100% tested. 6. ratiometric temperature coefficient = (v(r w ) t1(n) -v(r w ) t2(n) )/[v(r w ) t1(n) (t1-t2)] x 10 6 , with t1 & t2 being 2 temperatures, and n from 0 to 255. 7. measured with wiper at tap position 255, r l grounded, using test circuit. 8. t wc is the minimum cycle ti me to be allowed for any nonvolatile write by the us er, unless acknowledge polli ng is used. it is the t ime from a valid stop condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of cs of a valid ?store? operation of the up/down interface, to the end of the self-timed internal nonvolatile write cycle. 9. the recommended power up sequence is to apply v cc /v ss first, then the potentiometer voltages. during power up, the data sheet parameters for the dcp do not fully apply until t d after v cc reaches its final value. in order to prevent unwanted tap position changes, or an inadvertant store, bring the cs pin high before or concurrently with the v cc pin on power up. cs scl u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns ds0, ds1 high-voltage write cycle timing symbol parameter typ max units t wc (notes 5, 8) non-volatile write cycle time 5 10 ms xdcp timing symbol parameter min max units t wrl (note 5) scl rising edge to wiper code changed, wiper response time after instruction issued (all load instructions) 520s x9455
8 fn8202.1 july 28, 2006 test circuit equivalent circuit pin descriptions bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for the 2-wire interface. it receives device address, operation code, wiper register address and data from a 2-wire external master device at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. sda requires an external pull-up resistor, since it?s an open drain output. serial clock (scl) this input is the serial clock of the 2-wire and up/down interface. device address (a2-a0) the address inputs are used to set the least significant 3 bits of the 8-bit 2-wire interface slave address. a match in the slave address serial data st ream must be made with the address input pins in order to initiate communication with the x9455. a maximum of 8 devices may occupy the 2-wire serial bus. chip select (cs ) when the cs pin is low, increment or decrement operations are possible using the scl and u/d pins. the 2-wire interface is disabled at this time. when cs is high, the 2-wire interface is enabled. up or down control (u/d ) the u/d input pin is held high during increment operations and held low during decrement operations. dcp select (ds1-ds0) the ds1-ds0 select one of the four dcps for an up/down interface operation. hardware write protect input (wp ) when the wp pin is set low, ?write? operations to non volatile dcp data registers are disabled. this includes both 2-wire interface non-volatile ?write?, and up/down interface ?store? operations. dcp pins r h0 , r l0 , r h1 , r l1 these pins are equivalent to the terminal connections on mechanical potentiometers. si nce there are two dcps, there is one set of r h and r l for each dcp. r w0a , r w0b , r w1a , and r w1b the wiper pins are equivalent to the wiper terminals of mechanical potentiometers. since there are two wipers per dcp, there are four r w pins. force current test point r w c h c l r w r total c w r h r l x9455
9 fn8202.1 july 28, 2006 principles of operation the x9455 is an integrated circ uit incorporating two resistor arrays with dual wipers on each array, their associated registers and counters, and the serial interface logic providing direct communication between the host and the digitally controlled potentiomet ers. this section provides detail description of the following: ?resistor array ? up/down interface ? 2-wire interface resistor array description the x9455 is comprised of two resistor arrays. each array contains 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r hi and r li inputs). (see figure 1.) each array has two independent wipers. at both ends of each array and between each resistor segment are two switches, one connected to each of the wiper pins (r wia and r wib ). within each individual array only one switch of each wiper may be turned on at a time. these switches are contro lled by two wiper counter register (wcr). the 8-bits of the wcr are decoded to select and enable one of 256 switches. note that each wiper has a dedicated wcr. when all bits of a wcr are zeroes, the switch closest to the corresponding r l pin is selected. when all bits of a wcr are ones, the switch closest to the corresponding r h pin is selected. the wcrs are volatile and may be written directly. there are four non-volatile data re gisters (dr) associated with each wcr. each dr can be loaded into wcr. all drs and wcrs can be read or written. power up and down requirements during power up cs must be high to avoid inadvertant ?store? operations. at powe r up, the contents of data registers level 0 (dr0a0, dr0b0, dr1a0, and dr1b0), are loaded into the correspond ing wiper counter register. one of wcria[7:0] r hi r wia r li = ff hex 255 254 255 256 decoder volatile 8-bit wiper counter register wcria four non-volatile data registers dria0, dria1, dria2, and dria3 ?i? is either 0 or 1 wcrib[7:0] = 00 hex 1 0 r wib 254 0 1 wcrib[7:0] = ff hex wcria[7:0] = 00 hex volatile 8-bit wiper counter register wcrib four non-volatile data registers drib0, drib1, drib2, and drib3 2-wire and up/down interfaces . . . . . . figure 1. detailed block diagram of one dcp x9455
10 fn8202.1 july 28, 2006 up/down interface operation the scl, u/d , cs, ds0 and ds1 inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled to respond to the u/d and scl inputs. high to low transitions on scl will increment or decrement (depend ing on the state of the u/d input) a wiper counter register selected by ds0 and ds1. the output of this counter is decoded to select one of 256 wiper positions along the resistor array. the value of the counter is stor ed in nonvolatile data register level 0 of the corresponding wcr whenever cs transitions high while the scl and wp inputs are high (see table 1). during a ?store? operation bits wcrsel1 and wcrsel0 in the status register must be bo th ?0?, which is their power up default value. other combinations are reserved and must not be used. the system may select the x9455, move a wiper, and deselect the device without havi ng to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as described above and once the new position is reached, the system must keep scl low wh ile taking cs high. the new wiper position is maintained until changed by the system or until a pow er-down/up cycle recalled the previously stored data. this procedure allo ws the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. the 2-wire interface is disabled while cs remains low. *while in standby, the 2-wire interface is enabled table 1. dcp selection for up/down control ds1 ds0 selected wiper control register 0 0 wiper a of dcp0 1 1 wiper b of dcp0 1 0 wiper a of dcp1 0 1 wiper b of dcp1 table 2. mode selection for up/down control cs scl u/d mode l h wiper up l l wiper down h x store wiper position to nonvolatile memory if wp pin is high. no store, return to standby, if wp pin is low. h x x standby* l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended) x9455
11 fn8202.1 july 28, 2006 2-wire serial interface protocol overview the device supports a bidirect ional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. the x9455 operates as a slave in all applications. all 2-wire interface operations must begin with a start, followed by a slave address byte. the slave address selects the x9455, and specifies if a read or write operation is to be performed. all communication over the 2-wir e interface is conducted by sending the msb of each byte of data first. serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop conditions (see figure 2). on power up of the x9455, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met (see figure 2). serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus (see figure 2). serial acknowledge an ack (acknowledge), is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, rel eases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 3). the device responds with an ack after recognition of a start condition followed by a valid slave address byte. a valid slave address byte must contain the device type identifier 0101, and the device address bits matching the logic state of pins a2, a1, and a0 (see figure 4). if a write operation is select ed, the device responds with an ack after the receipt of eac h subsequent eight-bit word. in the read mode, the device transmits eight bits of data, releases the sda line, and then monitors the line for an ack. the device continues transmitting data if an ack is detected. the device terminates further data transmissions if an ack is not detected. the master must then issue a stop condition to place the device into a known state. sda scl start data data stop stable change data stable figure 2. valid data changes, start, and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master figure 3. acknowledge response from receiver x9455
12 fn8202.1 july 28, 2006 slave address byte following a start condition, the master must output a slave address byte (refer to figure 4.). this byte includes three parts: ? the four msbs (sa7-sa4) ar e the device type identifier, which must always be set to 0101 in order to select the x9455. ? the next three bits (sa3-sa1) are the device address bits (as2-as0). to access any part of the x9455?s memory, the value of bits as2, as1, and as0 must correspond to the logic levels at pins a2, a1, and a0 respectively. ? the lsb (sa0) is the r/w bit. this bit defines the operation to be performed on the device being addressed. when the r/w bit is ?1?, then a read operation is selected. a ?0? selects a write operation . nonvolatile write acknowledge polling after a nonvolatile write command sequence is correctly issued (including the final stop condition), the x9455 initiates an internal high vo ltage write cycle. this cycle typically requires 5 ms. during this time, any read or write command is ignored by the x9455. write acknowledge polling is used to determine whether a high voltage write cycle is completed. during acknowledge polling, the master first issues a start condition followed by a slave address byte. the slave address byte contains the x9455?s device type identifier and device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is busy within the high voltage cycle, then no ack is returned. if the high voltage cycle is completed, an ack is returned and the master can then proceed with a new read or write operation. (refer to figure 5.) 2-wire serial interface operation x9455 digital potentiometer register organization refer to the functional diagram on page 1. there are 2 digital potentiometers, referred to as dcp0, and dcp1. each potentiometer has two volatile wiper control registers (wcrs). each wiper has four non-volatile registers to store wiper position or general data. see table 2 for register numbering. sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read or sa4 slave address bit(s) description sa7-sa4 device type identifier sa3-sa1 device address sa0 read or write operation select r/w 0101 address device as0 as1 as2 write figure 4. slave address (sa) format ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes no continue normal read or write command sequence proceed yes complete. continue command sequence. high voltage issue stop figure 5. acknowledge polling sequence x9455
13 fn8202.1 july 28, 2006 the registers are organized in pages of four, with one page consisting of the four volatile wcrs, a second page consisting of the level 0 data registers, and so forth. these pages can be written four bytes at time. in this manner all four potentiometer wcrs can be updated in a single serial write (see page write operation), as well as all four registers of a given page in the dr array. the unique feature of the x9455 device is that writing or reading to a data register of a given wiper automatically updates the wcr of that wiper with the new value. in this manner data can be moved from a particular wiper register to that wiper?s wcr just by performing a 2-wire read operation. simultaneously, that data byte can be utilized by the host. status register organization the status register (sr) is used in read and write operations to select the appropriate wiper register. before any wiper register can be accessed, the sr must be set to the correct value. it is accesse d by setting the address byte to 07h. see table 3. do this by writing the slave address followed by a byte address of 07h. the sr is volatile and defaults to 00h on power up. it is an 8-bit register containing three control bits in the 3 lsbs as follows: bits wcrsel1 and wcrsel0 determine which data register of a wiper is selected for a gi ven operation. nvenable is used to select the volatile wcr if ?0?, and one of the non volatile wiper registers if ?1?. table 3 shows this register organization. wiper addressing for 2-wire interface once the data register level has been selected by a 2-wire instruction, then the wiper is determined by the address byte of the following instruction. note again that this enables a complete page write of all f our potentiometers at once a particular wiper register has been chosen. the register addresses accessible in the x9455 include: table 3. register numbering status reg (note 1) (addr: 07h) registered selected (note 2) reserved bits 7-3 drsel1 bit 2 drsel0 bit 1 nvenable bit 0 dcp0 dcp2 (addr: 00h) (addr: 11h) (addr: 02h) (addr: 01h) reserved x x 0 wcr0a wcr0b wcr1a wcr1b 0 0 1 dr0a0 dr0b0 dr1a0 dr1b0 0 1 1 dr0a1 dr0b1 dr1a1 dr1b1 1 0 1 dr0a2 dr0b2 dr1a2 dr1b2 1 1 1 dr0a3 dr0b3 dr1a3 dr1b3 notes:to read or write the contents of a single data register or wiper register: 1. load the status register (using a write command) to select the row. (see figure 6.) writing a 1, 3, 5, or 7 to the status register specifies that the subsequent read or write command will access a data register. this status register operation also initiates a transfer of the contents of the selected data register to its associated wcr for all dcps. so, for example, writing ?03h? to the status register causes the value in dr01 to move to wcr0, dr11 to move to wcr1, dr21 to move to wcr2, and dr31 to move to wcr3. writing a 0 to bit ?0? of the status regi ster specifies that the subsequent read or wr ite command will access a wiper counter r egister. each wcr can be written to individually, with out affecting the contents of any other. 2. access the desired dr or wcr using a new write or read command (see figure 7 for write and figure 9 for read.) specify the desired column (dcp number) by sending the dcp address as part of this read or write command. 76543 2 1 0 reserved wcrsel1 wcrsel0 nvenable x9455
14 fn8202.1 july 28, 2006 all other address bits in the address byte must be set to ?0? during 2-wire write operations and their value should be ignored when read. byte write operation for any byte write operation, the x9455 requires the slave address byte, an address byte, and a data byte (see figure 7). after each of them, the x9455 responds with an ack. the master then terminates t he transfer by generating a stop condition. at this time, if the write operation is to a volatile register (wcr, or sr), the x9455 is ready for the next read or write operation. if the write operation is to a nonvolatile register (dr), and the wp pin is high, the x9455 begins the internal write cycle to the nonvolatile memory. during the internal nonvolatile write cycle, the x9455 does not respond to any requests from the master. the sda output is at high impedance. the sr bits and wp pin determine the register being accessed through the 2-wire interface. see table 2 on page 9. as noted before, any write oper ation to a data register (dr), also transfers the contents of all the data registers in that row to their corresponding wcr. for example, to write 3ahex to the level 1 data register of wiper 1a (dr1a1) the following sequence is required: during the sequence of this example, wp pin must be high, and a0, a1, and a2 pins must be low. when completed, the dr1a1 register and the wcr1a of wiper 1a will be set to 3ah, and the other data registers in row 1 will transfer their contents to the respective wcrs. s t a r t s t o p slave address status register address data a c k a c k signal at sda signals from the slave signals from the master 0 a c k if bit 0 of data byte = 1, dr contents move to wcr during this ack period 0101 0 0 0 0 0 1 1 1 0 0 0 0 0 x x 1 dr select figure 6. status register write (uses standard byte write sequence to set up access to a data register) table 4. addressing for 2-wire interface address byte address (hex) contents 0 wiper 0a 1 wiper 1b 2 wiper 1a 3 wiper 0b 4 not used 5 not used 6 not used 7 status register start slave address 0101 0000 ack address byte 0000 0111 ack data byte 0000 0011 ack (note: at this ack, the wcrs are all updated with their respective dr.) stop start slave address 0101 0000 ack address byte 0000 0010 ack data byte 0011 1010 ack stop (hardware address = 000, and a write command) (indicates status register address) (data register level 1 and nvenable selected) (hardware address = 000, (access wiper 1a) (write data byte 3ah) write command) x9455
15 fn8202.1 july 28, 2006 page write operation as stated previously, the memory is organized as a single status register (sr), and four pages of four registers each. each page contains one data register for each wiper. normally a page write operation will be used to efficiently update all four data registers and wcr in a single write command. note the special sequence for writing to a page: first wiper 0a, then 1b, then 1a, then 0b as shown in figure 9. in order to perform a page write operation to the memory array, the nvenable bit in the sr must first be set to ?1?. a page write operation is initia ted in the same manner as the byte write operation; but in stead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 4 bytes (see fi gure 9). after the receipt of each byte, the x9455 responds with an ack, and the internal wcr address is incremented by one. the page address remains constant. when the address reaches the end of the page, it ?rolls over? and goes back to the first byte of the same page. for example, if the master writes three bytes to a page starting at location dr1a2, the first two bytes are written to locations dr1a2 and dr0b2, while the last byte is written to location dr0a2. afterwards, the wcr address would point to location dr1b2. if the master supplies more than four bytes of data, then new data ov erwrites the previous data, one byte at a time. the master terminates the loading of data bytes by issuing a stop condition, which initiate s the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. if the wp pin is low, the nonvolatile write cycle does n?t start and the bytes are discarded. notice that the data bytes are also written to the wcr of the corresponding wcrs, therefore in the above example, wcr1a, wcr0b, and wcr0a are also written, and wcr1b is updated with the contents of dr1b2. s t a r t s t o p slave address address byte data byte a c k signals from the master signals from the slave a c k 0 0 0 11 a c k write signal at sda figure 7. byte write sequence wcr wcr0a wcr1b wcr1a wcr0b dr level 0 dr0a0 dr1b0 dr1a0 dr0b0 dr level 1 dr0a1 dr1b1 dr1a1 dr0b1 dr level 2 dr0a2 dr1b2 dr1a2 dr0b2 dr level 3 dr0a3 dr1b3 dr1a3 dr0b3 figure 8. page write sequence* *page writes may wrap around to the first address on a page from the last address. 2 < n < 4 signals from the master signals from the slave signal at sda s t a r t slave address address byte a c k a c k 0 0 0 11 data byte (1) s t o p a c k a c k data byte (n) write figure 9. page write operation x9455
16 fn8202.1 july 28, 2006 move/read operation the move/read operation simultaneously reads the contents of a data register and moves the contents into the corresponding dcp?s wcr and all wipers will have their wcr?s updated with the data register values from the row that was read. move/read operation consists of a one byte, or three byte instruction followed by one or more data bytes (see figure 10). to read an arbitrary byte, the master initiates the operation issuing the following sequence: a start, the slave address byte with the r/w bit set to ?0?, an address byte, a second start, and a second slave address byte with the r/w bit se t to ?1?. after each of the three bytes, the x9455 responds with an ack. then the x9455 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminat es the move/read operation (issuing a stop condition) following the last bit of the last data byte. the first byte being read is determined by the current wiper address and by the status regist er bits, according to table 1 on page 11. if more than one byte is read, the wcr address is incremented by one after each byte, in the same way as during a page write operation. after reaching wcr0b, the wcr address ?rolls over? to wcr0a. on power up, the address pointer is set to the data register 0 of wcr0a. signals from the master signals from the slave signal at sda s t a r t slave address with r/w =0 address byte a c k a c k 0 0 0 11 s t o p a c k 0 1 0 11 slave address with r/w =1 a c k s t a r t last read data byte first read data byte a c k one or more data bytes current address read setting the current address random address read figure 10. move/read sequence x9455
17 fn8202.1 july 28, 2006 applications information basic configurations of electronic potentiometers application circuits v r rw0 four terminal potentiometer; variable voltage divider four-wiper dcp rw1 rw0a rw0b rw1a rw1b pot0 pot1 rh rl poti window comparator shunt limiter function generator + - v s v o v+ + - v ul v ll v+ + - v s v o } } v r + } mr nr pr + - v o } } } mr nr pr c + - x9455
18 fn8202.1 july 28, 2006 programmable state variable filter + - v o (bp) } } } mr1 nr1 pr1 c v s + - v o (lp) } } } mr2 nr2 pr2 c + - r3 v o (hp) programmable ladder networks } } } mr nr pr r1 c1 a2 a1 a3 + - v o } c2 r 4 c1 } r 3 } r 2 } r 1 r w3 r w2 r w1 wien bridge oscillator + - + - r 3 r 4 r 5 two wiper dcp z 1 z 2 z in = z 1 z 2 r 3 * r 5 r 4 ( ) * generalized impedance converter x9455
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8202.1 july 28, 2006 x9455 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol 14 ld 16 ld 20 ld 24 ld 28 ld tolerance a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. e 12/02 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
x9455 printer friendly version dual two-wiper digitally-controlled (xdcp?) potentiometer datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ x9455tv24i-2.7 active ind 24 ld tssop 1 3.65 x9455tv24iz-2.7 active ind 24 ld tssop 3 3.65 x9455us24i-2.7 active ind 24 ld soic 5 3.59 x9455us24iz-2.7 active ind 24 ld soic 5 3.59 x9455uv24i-2.7 active ind 24 ld tssop 1 3.65 x9455uv24iz-2.7 active ind 24 ld tssop 3 3.65 x9455ws24i-2.7 active ind 24 ld soic 5 3.59 x9455ws24iz-2.7 active ind 24 ld soic 5 3.59 x9455wv24i-2.7 active ind 24 ld tssop 1 3.65 x9455wv24iz-2.7 active ind 24 ld tssop 3 3.65 x9455ys24i-2.7 active ind 24 ld soic 5 3.59 x9455ys24iz-2.7 active ind 24 ld soic 5 3.59 x9455yv24i-2.7 active ind 24 ld tssop 1 3.65 x9455yv24iz-2.7 active ind 24 ld tssop 3 3.65 xlabview01 active n/a 91.77 xlabview01z active eval board n/a 91.77 X9455WP24I inactive ind 24 ld pdip n the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the x9455 integrates 2 digitally controlled potentiometers (xdcp), each one with dual wipers, on a monolithic cmos integrated circuit. the digitally controlled potentiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to wiper terminals through switches. the position of each wiper on the array is controlled by the user through the u/d or 2-wire bus interface. each potentiometer wiper has associated with it two volatile wiper counter register (wcr) and each wcr has associated with it four nonvolatile data registers that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. the contents of the default data registers (dr0a0, dr0b0, dr1a0, dr1b0) are loaded into the wcr on power up. the dcp can be used as a four-terminal potentiometer in a wide variety of applications including the programming of bias voltages, window comparators, and three resistor programmable networks. key f eatures
dual two-wiper solid state potentiometer 256 resistor tap points?0.4% resolution 2-wire serial interface for write, read, and transfer operations of the potentiometer up/down interface for individual potentiometer wipers wiper resistance, 40 typical non-volatile storage of wiper positions power on recall loads saved wiper position on power up. standby current < 20a max maximum wiper current: 3ma v cc : 2.7v to 5.5v operation 2.8k , 10k , 50k , 100k version of total pot resistance endurance: 100,000 data changes per bit per register 100 yr. data retention 24-lead tssop related documentation application note(s): a compendium of application circuits for intersil?s digitally-controlled (xdcp) potentiometers a primer on digitally-controlled potentiometers application of intersil digitally controlled potentiometers (xdcp?) as hybrid analog/digital feedback system control elements dc/dc module trim with digital potentiometers designing power supplies using intersil?s xdcp mixed signal products power supply and dc to dc converter control using intersil digitally controlled potentiontiometers (xdcps) putting analog on the bus shaft encoder drives multiple intersil digitally controlled potentiontiometers (xdcps) tone, balance, and volume control using a quad xdcp datasheet(s): dual two-wiper digitally-controlled (xdcp?) potentiometer technical brief(s): converting a fixed pwm to an adjustable pwm evaluation board(s): intersil_xdcp_test_utility_manual_rev_3.2.3.pdf labview_xdcp_software.zip labview_xdcp_upgrade_3.2.3.zip readme_xicorlabview_v3.2.3.txt xdcp_vref evaluation board kit documentation and software accesshw.zip technical homepage: digitally controlled potentiometers (dcps) and capacitors (dccs) precision analog homepage parametric data number of dcps dual number of taps 256 memory type non-volatile bus interface type 2-wire, 3-wire (up-down) resistance options (k ) 2, 10, 50, 100 v cc range (v) 2.7 to 5.5 dcp differential terminal voltage (v) 0 to +5.5 terminal voltage range v l to v h (v) 0 to v cc resistance taper linear wiper current (ma) 3 wiper resistance ( ) 150 standby current i sb ( a) 20 related devices parametric table
isl22323 dual digitally controlled potentiometer (xdcp?), low noise, low power, i 2 c? bus, 256 taps isl22424 dual digitally controlled potentiometer (xdcp?), low noise, low power, spi? bus, 256 taps x9260 dual digitally controlled (xdcp?) potentiometers x9261 dual digitally controlled (xdcp?) potentiometers x9268 dual digitally controlled (xdcp?) potentiometers x9269 dual digitally controlled (xdcp?) potentiometers x95820 dual digital controlled potentiometers (xdcp?); low noise/low power/2- wire bus/256 taps about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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